The present invention generally relates to xe2x80x9csilicon-on-insulatorxe2x80x9d (SOI) technology in which the semiconductor devices such as CMOS and bipolar transistors in a device layer are spaced apart from underlying conducting or semiconducting substrate layers to reduce substrate capacitance effects. More particularly, this invention relates to a method for forming a transferable device-containing layer that may be bonded to any type of substrate, and to the use of this method for forming integrated multifunctional systems-on-a-chip on insulating substrates. A second aspect of the invention relates to methods for separating a semiconductor layer from a substrate, and more particularly to ELTRAN (Epitaxial Layer TRANsfer)-related methods for forming and breaking apart a porous layer which initially connects or is between the semiconductor layer and substrate.
As semiconductor devices shrink to smaller dimensions, device speeds increase and substrate capacitance effects become an increasingly large contributor to device cycle times. This problem is typically addressed by building xe2x80x9csilicon on insulatorxe2x80x9d (SOI) devices, where a thin (xcx9c200 nm), single crystal Si device layer containing the devices is situated on an insulating substrate layer or substrate instead of directly on Si. It should be noted that for the purposes of this invention, we use the term xe2x80x9cdevice layerxe2x80x9d to refer to the (nominally) single crystal semiconductor layer in which devices may be built, and that at different times during processing a given device layer may or may not actually have devices in it.
While semiconductor device layers can be grown epitaxially on single-crystal insulating substrates, xe2x80x9cSilicon On Sapphirexe2x80x9d (SOS) being a prime example, semiconductor device layers are more typically formed in a Buried OXide (BOX) geometry, in which an amorphous oxide (typically SiO2) is sandwiched between a thin semiconductor device layer and a Si wafer substrate. BOX geometry wafers may be produced by xe2x80x9cSeparation by IMplantation of OXygenxe2x80x9d (SIMOX), where a buried SiOx layer is formed by ion implantation of oxygen, and the device layer through which the ions have passed is repaired by a recrystallization anneal.
BOX approaches also include several wafer bonding techniques. In conventional bonding terminology, which we will use here, an epitaxial device layer is grown on a sacrificial xe2x80x9cseed wafer.xe2x80x9d The device layer is then detached from the seed wafer after it is bonded to a xe2x80x9chandle waferxe2x80x9d which will accompany the device layer through the processing steps needed to fabricate the devices. Bonding techniques for BOX SOI include (i) Smart-Cut(copyright) (where H implants are used to separate the device layer from the seed wafer after the device layer is bonded to a surface oxide on the handle wafer), (ii) BESOI (xe2x80x9cBond-Etchback SOI,xe2x80x9d where the seed wafer is removed by etching after the device layer is bonded to an oxide layer on the handle wafer), and (iii) ELTRAN (xe2x80x9cEpitaxial Layer TRANsfer,xe2x80x9d where the seed wafer contains a porous Si layer on which the device layer is first grown, then partially oxidized, and then finally bonded to the handle wafer, after which the device layer is separated from the seed wafer by a collimated water jet which breaks apart the porous Si layer. These and other wafer bonding methods are described in U.S. Pat. No. 5,710,057, issued Jul. 12, 1996 to D. M. Kenney. Smart-Cut(copyright) process is described in U.S. Pat. No. 5,374,564 by M. Bruel which issued Dec. 20, 1994 and in U.S. Pat. No. 5,882,987 by K. V. Srikrishnan which issued Mar. 16, 1999. BESOI SOI is described in U.S. Pat. No. 5,906,951 by Chu et al. which issued May 25, 1999.
However, a problem with using SOI substrate wafers made by these techniques is that the processing to form the devices in the device layer is done after the device layer has been bonded to (or grown on) a handle wafer which also acts as the final substrate for the devices. The handle wafer must thus be able to survive the processing steps required to form the devices (e.g., activation anneals, etc.).
Unfortunately, few wafer substrate materials are sufficiently compatible with the high temperatures and temperature cycling of Si processing. Highly insulating ( greater than 1 kxcexa9-cm) Si wafer substrates are potentially suitable substrates, but they are expensive and easily warped (a problem for lithography) compared to conventional lightly doped (10 to 100 xcexa9-cm) Si wafers. Sapphire wafer substrates are also expensive, and present concerns about thermal expansion mismatches between Si and sapphire (Al2O3). In addition, the epitaxially-grown Si layers in SOS wafers typically have a high density of defects, due to imperfect lattice matching of the Si and sapphire (Al2O3).
BOX approaches typically use lightly doped Si wafer substrates with a buried SiO2 layer as the insulator. While the Si wafer substrate is completely compatible with Si device processing, the SiO2 layer must be thin, both to reduce thermal mismatch stresses to the Si device layer during processing, and to prevent thermal isolation of the device layer (and device heating) during device operation. BOX approaches using SiO2 as the buried oxide are thus of limited value in spacing apart the device layer from the Si wafer substrate. More thermally conductive materials such as Al2O3, AlN, or diamond may be used as a thicker insulating xe2x80x9cBOXxe2x80x9d layer, but concerns about thermal expansion mismatches again remain.
These difficulties with building SOI devices on SOI substrate wafers can be circumvented by transferring the device layer to the substrate of choice after the devices have been formed in the device layer. Previous implementations of this approach include (i) U.S. Pat. No. 5,877,034, xe2x80x9cMethod of making a three-dimensional integrated circuit,xe2x80x9d issued Mar. 2, 1999 to Ramm and Buchner, which describes fabricating a device-containing device layer (including optional interconnection layers) on a first substrate, transferring device layer to an auxiliary substrate, removing the first substrate by a xe2x80x9cthickness reductionxe2x80x9d process comprising polishing or grinding, bonding the device to a final substrate, and, finally, removing the auxiliary substrate, and (ii) U.S. Pat. No. 5,674,758, xe2x80x9cSilicon on insulator achieved using electrochemical etching,xe2x80x9d issued Oct. 7, 1997 to McCarthy, which describes forming a device-containing device layer on a first substrate, transferring it to a final substrate, and removing the first substrate by standard etching techniques in combination with electrochemical etching techniques. However, these approaches require a sacrificial wafer which cannot be reused, as well as stringent endpoint control to avoid continuing the sacrificial wafer etch into the device layer. The use of a sacrificial release layer between the device-containing device layer and its original substrate allows reuse of the original substrate. This sacrificial release layer approach, exemplified by U.S. Pat. No. 5,528,397, xe2x80x9cSingle crystal silicon transistors for display panels,xe2x80x9d issued Jun. 18, 1996 to Zavracky et al., typically requires a thermally stable release layer (e.g., SiO2), and the use of channels or grooves in the device layer to provide a path for the etchant to reach and dissolve away the release layer. However, the need for grooves, and concerns about device damage from the release layer etchant are disadvantages of this approach. It would therefore be desirable to have an improved method for transferring device-containing device layers from one substrate to another.
BOX approaches to forming SOI wafer substrates that are based on bonding a semiconductor device layer to a handle wafer require a method for separating a semiconductor layer from the seed wafer substrate. In the prior art ELTRAN process, separation is accomplished by breaking apart a porous layer which initially connects the semiconductor layer to the seed wafer substrate. A schematic of the ELTRAN process based on the description of K. Sakaguchi and T. Yonehara in Solid State Technology, June 2000, p. 88 is shown in FIGS. 1A-1G. FIG. 1A shows silicon seed wafer 10 after formation of porous silicon layer 20. A high-quality epitaxial Si layer 30 (the device layer) is then grown on porous silicon layer 20 to form the structure of FIG. 1B. A portion of silicon layer 30 is then thermally oxidized to form thermal oxide layer 40 shown in FIG. 1C. The structure of FIG. 1C is then bonded to Si handle wafer 50 to form the 2-wafer structure of FIG. 1D. Porous Si layer 20 is then split by a pressurized water jet 60, as shown in FIG. 1E, to form the structure of FIG. 1F with handle wafer 50, thermal oxide layer 40, device layer 30, and residual porous Si layer 20xe2x80x2. FIG. 1G shows the final SOI structure obtained after removing residual porous Si layer 20xe2x80x2, and etching/annealing the device layer to make it smooth and flat.
While this traditional ELTRAN approach to forming SOI wafer substrates has been successfully demonstrated, several aspects are open to improvement. To ensure a porous silicon layer that can be cleanly broken, ELTRAN typically employs a double layer of porous silicon comprising a first porous Si layer with a first porosity, and a second porous Si layer with a different porosity. High stress concentrations are present at the interface between the two porous Si layers, an arrangement that facilitates wafer splitting, since wafer splitting will relieve the stress. However, it can be difficult to engineer the appropriate stress differentials so that the porous silicon is weak enough to split with the water jet yet strong enough to survive processing. It would be desirable to have another method of designing porous Si-based layers that can be easily and controllably split apart. Another concern with the traditional ELTRAN approach is water jet alignment; careful alignment is needed to ensure that the water jet impinges only on the porous silicon layer and does not attack the device layer or seed wafer surface. It would be desirable to have a splitting process that does not require any alignment.
In view of the above-described circumstances it is therefore an object of this invention to provide an improved method for forming structures comprising thin device-containing device layers on insulating or specialty substrates selectable without regard to the substrate""s compatibility with silicon processing.
It is a further object of this invention to provide a thin device-containing device layer on an insulating or specialty substrate for use as an integrated multifunctional system-on-a-chip.
It is an additional object of this invention to provide an alternative to the ELTRAN method for separating a semiconductor layer from a substrate, and more particularly to improved methods for forming and splitting or breaking apart the porous layer by which the semiconductor layer and substrate are initially joined or connected.
The present invention provides an improved method for forming structures containing device-containing device layers that have been transferred from one substrate to another. The method comprises a novel combination of (i) prior art concepts for forming structures containing transferred device-containing device layers, (ii) prior art methods for building device-containing device layers, and (iii) the prior art ELTRAN technique for separating a device-free device layer from its original substrate. In one method of the present invention, a semiconductor device layer (e.g., one or more layers of strained or unstrained Si or silicon germanium) is initially grown on a first (seed) substrate containing an at least partially crystalline porous release layer. The device layer is then processed to form a device-containing device layer (which may include isolation regions and interconnects, if desired). The device-containing device layer is next separated from its seed wafer substrate by splitting or breaking apart the porous release layer. This separation step may occur before or after the device layer is bonded to its final substrate (with separation before bonding to the final substrate requiring the use of an additional temporary carrier substrate). This novel use of ELTRAN for separating a device-containing device layer from its substrate requires that the porous release layer survive the device-forming processing steps. In particular, the porous release layer should have sufficient thermal and mechanical stability to not release prematurely or lose its releasing properties during process steps such as high temperature activation anneals and chemical mechanical polishing. These properties of porous silicon were not required or anticipated to be necessary for the original ELTRAN invention, and the best mode of the present invention may require stronger formulations of the porous layer material/structure and more powerful methods for splitting or breaking the porous layer apart.
Like prior methods for forming structures comprising device-containing device layers that have been transferred from one substrate to another, the present method has the advantage that the thin device-containing layer can be bonded to almost any substrate without regard to the substrate""s compatibility with Si device manufacturing. In particular, the final substrate may be selected to optimize any one or more of the following properties: mechanical flexibility, electrical resistance, cost, weight, environmental impact, thermal conductivity, cooling power including passive cooling and active cooling.
Another aspect of the present invention pertains to an alternative method for device layer/wafer separation. As in ELTRAN, the epitaxial device layer is grown on a porous Si layer between the semiconductor layer and seed wafer substrate, although with the additional restriction that the porous Si layer be designed to have an open porosity. The device layer (with or without devices in it) is separated from the substrate by breaking up the porous layer with a freeze-thaw technique in which a fluid like water is introduced into the pores and expanded by freezing.
Yet another aspect of the present invention pertains to replacing the porous Si layer with a porous silicon germanium alloy (e.g., Si1-xGex, where 0 less than x less than 1 may be constant or spatially variable) or at least one porous silicon germanium alloy layer in combination with porous Si. This provides additional flexibility in designing interface strain within the porous release layer, since SiGe layers with different Ge content will have different strains as well as different responses to the anodic etching processes typically employed to induce porosity.